1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having diagonal direction wiring, and a layout method therefor, and more particularly to a semiconductor integrated circuit device and a layout method therefor in which the width of the diagonal direction wiring can be narrowed, thereby enabling an increase in the density of the diagonal direction wiring.
2. Prior Art
A semiconductor integrated circuit device (LSI) is a large-scale circuit constituted by connecting a plurality of circuit elements formed on a semiconductor substrate with wires in a multi-layer wiring layer on the substrate. The number of wires in this multi-layer wiring layer is great, and hence layout of the wires is usually performed automatically using an automatic layout tool controlled by a computer program rather than manually. In the layout performed by this automatic layout tool, wires extending in a vertical direction and a horizontal direction are combined to form connecting wires between the circuit elements.
This automatic layout method is based on a grid architecture and a preferred direction. In the grid architecture, wires are formed in a horizontal direction and vertical direction over a standard grid which is defined at a constant pitch in the horizontal and vertical directions. Hence all of the wires are disposed on the standard grid at intervals of integral multiples of the grid pitch, and, as a result, algorithms for data processing, wire retrieval, and so on can be simplified. A preferred direction, on the other hand, is an architecture in which wires only in a vertical direction are formed on a first wiring layer, and wires only in a horizontal direction are formed on a second wiring layer above or below the first wiring layer. By limiting the wiring directions in each wiring layer, the automatic layout algorithms can be simplified.
In these layout architectures, the wiring is invariably positioned on a grid and connection points connecting the wires of different layers are positioned at grid points, and thus such architectures have the merit of enabling simplification of the automatic layout algorithms.
However, in these architectures, circuit elements are connected only by a combination of wires in a horizontal direction and vertical direction, and hence the wiring tends to increase in length, delay times caused by the wiring configuration increase, and it is sometimes difficult to form a critical pass with severe restrictions on the signal timing. Hence in recent years, an architecture which allows diagonal wiring with a 45° or 135° incline in relation to the standard grid has been proposed, for example in Japanese Unexamined Patent Application Publication 2000-82743, Japanese Unexamined Patent Application Publication 2001-142931, and so on.
By allowing the formation of diagonal wiring, the length of the wires can be reduced, flexibility for the formation of the critical pass can be increased, and the layout capability of automatic layout can be greatly improved.
In Japanese Unexamined Patent Application Publication 2000-82743, the formation of diagonal wiring on a diagonal wiring grid is proposed, whereby in addition to a standard horizontal direction and vertical direction wiring grid, a diagonal wiring grid having a pitch of √2 P in relation to the pitch P of the standard wiring grid is provided so that a diagonal wiring is formed on the diagonal wiring grid. According to this method, the grid points on the standard wiring grid and the grid points on the diagonal wiring grid match, and hence vias for connecting different wiring layers can be limited to positions on the grid points, enabling simplification of the automatic layout algorithms.
In Japanese Unexamined Patent Application Publication 2001-142931, a proposal is made to employ a diagonal wiring grid similar to that described above, in which a first conductive layer having the wire width of the horizontal or vertical wires, a second conductive layer having the wire width of the diagonal wires, and a connection pattern comprising vias between the first and second conductive layers are provided at the connection points where the diagonal wires overlap with the horizontal or vertical wires. In other words, it is proposed that the diagonal wire width be set to √2 W in relation to the horizontal or vertical wire width W, and accordingly that the via figure be set to the width W on the horizontal or vertical wiring side, and to √2 W on the diagonal wiring side.
FIG. 1 is a view showing the example of diagonal wiring proposed in Japanese Unexamined Patent Application Publication 2000-82743, as described above. In the drawing, the dot/dash lines correspond to the standard grid and the diagonal grid. Vertical direction wires 10 are formed on the standard grid, and diagonal wires 12 are formed on the diagonal grid. By setting the pitch of the diagonal grid to √2 P in relation to the pitch P of the standard grid, the grid points of the two grids match, and vias 14 can be formed at the matching grid points.
FIG. 2 is a view showing a gridless architecture. In this gridless architecture, the pitch of a grid for diagonal wiring is set to be equal to the pitch P of the standard grid, enabling an increase in the density of the diagonal wires. However, the grid points 16 of the two grids do not match whatsoever, creating complications in the automatic layout algorithms. Such an architecture is impracticable, and hence unfavorable.